The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique which is effectively applicable to a semiconductor device which is manufactured by forming a plurality of respective semiconductor elements on a plurality of semiconductor element forming regions of a semiconductor wafer.
A plurality of respective semiconductor elements are formed on a plurality of semiconductor element forming regions of a semiconductor wafer and, thereafter, the semiconductor wafer is cut in a lattice shape using a dicing saw so as to separate respective semiconductor elements whereby a large number of semiconductor chips are formed from a sheet of semiconductor wafer.
Recently, to reduce a manufacturing cost of semiconductor chips by increasing the number of semiconductor chips manufactured from one sheet of semiconductor wafer, the semiconductor wafer in use has a diameter thereof large-sized. When the diameter of the semiconductor wafer is increased, the influence of a warp of the semiconductor wafer is increased. When the warp of the semiconductor wafer is increased, there arise various drawbacks. For example, at the time of exposing a photo resist film in a photolithography step, an alignment becomes difficult. Further, there exists a fear that the semiconductor wafer is broken down or cracks occur in the semiconductor wafer at the time of transporting the semiconductor wafer. Further, in a dicing step, the semiconductor wafer is cut in a state that the semiconductor wafer is adhered using a tacky adhesive tape and the semiconductor wafer is separated into respective semiconductor chips by stretching the tape. However, a stress applied to the semiconductor wafer is increased at the time of stretching the tape thus giving rise to chipping. These phenomena reduce a manufacturing yield rate of the semiconductor device and push up a manufacturing cost. Further, the reliability of semiconductor device is reduced. Accordingly, a technique to suppress a warp of the semiconductor wafer is becoming more important.
Japanese Unexamined Patent Publication No. Hei 10(1998)-83976 discloses a technique in which grooves are formed in scribe lines before forming transistors so as to prevent the occurrence of chip cracking and the displacement of dicing at the time of dicing. Further, Japanese Unexamined Patent Publication No. Hei 11(1999)-186119 discloses a technique which forms grooves in scribe lines so as to prevent a warp of a semiconductor wafer.
However, in the above-mentioned publication, an alignment pattern of a photolithography step is not taken into consideration at all. Accordingly, in the techniques disclosed in the above-mentioned publications, it is difficult to perform fine machining or processing. It is difficult to form the alignment pattern on bottom portions of grooves formed in the scribe lines. Even if the alignment pattern could be formed, it is difficult to accurately read the alignment pattern. Further, when the alignment pattern is formed on each semiconductor element forming region of the semiconductor wafer, the number of semiconductor chips which can be manufactured from a sheet of semiconductor wafer is reduced so that a manufacturing cost of the semiconductor devices is increased. Further, in the above-mentioned techniques disclosed in the above-mentioned publications, a step of forming the grooves in the scribe lines becomes necessary as an additional step and hence, the manufacturing steps of the semiconductor device is increased thereby increasing a manufacturing cost.
Accordingly, it is an object of a present invention to provide a semiconductor device and a manufacturing method thereof which can improve drawbacks attributed to a warp of a semiconductor wafer.
It is another object of the present invention to provide a semiconductor device and a manufacturing method thereof which enable fine processing.
It is still another object of the present invention to provide a semiconductor device and a manufacturing method thereof which can reduce a manufacturing cost.
It is still another object of the present invention to provide a semiconductor device and a manufacturing method thereof which can enhance a manufacturing yield rate.
It is still another object of the present invention to provide a semiconductor device and a manufacturing method thereof which can enhance the reliability.
The above-mentioned and other objects and novel features of the present invention will become apparent from the description of this specification and attached drawings.
To briefly explain the summary of typical inventions among inventions disclosed in the present application, they are as follows.
The present invention is characterized in that in scribe regions which are formed between a plurality of semiconductor element forming regions of a semiconductor substrate, the grooves are formed in the scribe regions except for alignment pattern forming regions such that the alignment pattern forming regions remain.
Further, the present invention is characterized in that at the time of forming gate trenches of a semiconductor element having a trench type gate structure by etching, grooves are formed in scribe regions of a semiconductor substrate.
There is provided a semiconductor device comprising:
a semiconductor substrate;
a plurality of semiconductor elements which are formed on a plurality of semiconductor element forming regions of the semiconductor substrate; and
grooves which are formed in the scribe regions such that alignment pattern forming regions remain in the scribe regions defined between the plurality of semiconductor element forming regions of the semiconductor substrate.
In the semiconductor device, in the scribe regions, the alignment pattern forming regions remain like islands inside the grooves.
In the semiconductor device, in the scribe regions, the alignment pattern forming regions remain like bridges inside the grooves.
In the semiconductor device, the grooves are formed in a grid array on a main surface of the semiconductor substrate.
In the semiconductor device, the grooves have a tapered shape.
In the semiconductor device, the plurality of semiconductor elements include semiconductor elements having a trench-type gate structure.
In the semiconductor device, the grooves have a depth greater than a depth of gate-use trenches of the semiconductor elements having the trench-type gate structure.
In the semiconductor device, a width of the grooves is greater than a film thickness of a gate electrode material films of the semiconductor elements having the trench-type gate structure.
In the semiconductor device, a width of the grooves is two or more times of a film thickness of gate electrode material films of the semiconductor elements having the trench-type gate structure.
In the semiconductor device, the semiconductor substrate includes a semiconductor substrate layer and an epitaxial layer formed over the semiconductor substrate layer, and the grooves penetrate the epitaxial layer and reach the semiconductor substrate layer.
In the semiconductor device, the plurality of semiconductor elements include field effect transistors.
In the semiconductor device, the plurality of semiconductor elements include bipolar transistors.
There is provided a semiconductor device comprising:
a semiconductor substrate;
a plurality of semiconductor elements which are formed on a plurality of semiconductor element forming regions of the semiconductor substrate and include vertical MISFETs having a trench-type gate structure; and
grooves which are formed in scribe regions defined between the plurality of semiconductor element forming regions of the semiconductor substrate.
In the semiconductor device, the grooves have a depth larger than a depth of gate-use trenches of the vertical MISFETs having the trench-type gate structure.
In the semiconductor device, the semiconductor substrate includes a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate layer, and the grooves penetrate the epitaxial layer and reach the semiconductor substrate layer.
In the semiconductor device, a width of the grooves is larger than a width of gate-use trenches of the vertical-type MISFETs having the trench-type gate structure.
In the semiconductor device, the grooves have a tapered shape.
In the semiconductor device, a width of the grooves is two or more times of a film thickness of gate electrode material films of the vertical-type MISFETs having the trench-type gate structure.